Technical Field
The present invention relates to a semiconductor storage field, and more particularly to a programming mode for improving the reliability of a multi-layer storage flash memory device in a solid-state hard disk controller, a flash memory controller, and the like, where the flash memory device is used as a storage medium.
Related Art
Different from a single-layer storage flash memory, a storage unit of a multi-layer storage flash memory device can save multi-bit logic information through setting multiple groups of threshold voltages, so as to significantly increase the storage capacity of the flash memory device without increasing hardware overhead. With the advantages of a high integration degree and low cost, the multi-layer storage flash memory device becomes the mainstream for flash memory devices.
To save multi-bit data in one same storage unit, a storage unit in a multi-layer storage flash memory need several times of programming, as shown in FIG. 1. When a write operation only needs to be performed on a most significant bit (MSB) bit in the multi-layer storage flash memory, the multi-layer storage flash memory directly transfers from an erasing state “E” to a second programming state “D2”, which requires the least time for programming. When a write operation is performed on an LSB page in the multi-layer storage flash memory, the multi-layer storage flash memory switches from the erasing state “E” to a first programming state “D1”. When the multi-layer storage flash memory needs to change the states of the MSB and LSB bits, the programming work is completed through two rounds of operations: in the first round operation, the erasing state “E” is first switched to the first programming state “D1”, and in the second round operation, the first programming state “D1” is then switched to the third programming state “D3”.
An array structure inside the multi-layer storage flash memory is shown in FIG. 2. An MSB bit and an LSB bit of a physical unit in the multi-layer storage flash memory are mapping into an MSB page and an LSB page, respectively. The physical unit in line WL0 is mapped into pages 0, 1, 4, and 5, respectively, in which page 0 and page 1 are MSB pages, whereas page 4 and page 5 are LSB pages. The physical unit in line WL1 is mapped into pages 2, 3, 8, and 9, respectively, in which page 2 and page 3 are MSB pages, whereas page 8 and page 9 are LSB pages. In this manner, in the last line WL63, page 250 and page 251 are MSB pages, whereas page 254 and page 255 are LSB pages.
A severe floating gate coupling effect exists in a flash memory device smaller than 45 nm. As shown in FIG. 3, the change of a floating gate voltage of a storage unit in the flash memory array causes a disturbance to a floating gate voltage of an adjacent storage unit, resulting in unexpected flipping of data saved in the adjacent storage unit.
Such a floating gate coupling effect in the flash memory device severely interferes with data saved in the flash memory. Especially for a multi-layer storage flash memory, because storage units require several times of programming, the influences caused by the floating gate coupling effect are severer. The reliability of a multi-layer storage flash memory is far lower than that of a conventional single-layer storage flash memory. Therefore, a reliability enhancement technology needs to be adopted in a flash memory controller to constrain the error rate of the multi-layer storage flash memory and prolong the service life of a device.